法人別リリース

Taiyo Holdings Launches Next-generation Semiconductor-packaging Material "FPIM Series," Achieving...

Taiyo Holdings — Thu, 10 Sep 2026 16:00:00 +0900

TOKYO, Sept. 10, 2026 /Kyodo JBN/ --
Taiyo Holdings Co., Ltd.
Taiyo Holdings Launches Next-generation Semiconductor-packaging Material "FPIM Series," Achieving Its First Three-layer RDL Formation with 700-nm CD on 12-inch Wafers

- Paper Presented at IEEE ESTC 2026, International Conference on Semiconductor- and Electronic Device-packaging Technologies and Related Materials -

Taiyo Holdings Co., Ltd. (Securities code: 4626; hereinafter "Taiyo Holdings"), based in Tokyo, presented a paper on September 10, 2026, at the 11th IEEE Electronics System-Integration Technology Conference (IEEE ESTC 2026), held in Helsinki, Finland, on the "FPIM Series" (hereinafter the "Material"), a next-generation semiconductor-packaging material. The FPIM Series is a fine-pitch RDL (*1) negative-tone i-line photosensitive insulating material for dual damascene processes.

This paper was co-authored with imec, one of the world’s largest semiconductor research institutes. The RDL is a key technology in advanced semiconductor-packaging structures, enabling more efficient electrical connections. Currently, RDLs are manufactured mainly using the semi-additive process (SAP) (*2). According to imec, as the industry pursues increasingly fine-pitch wiring, the dual damascene process (*3) will become essential for forming wiring with pitches of 1.6 micrometers or less. To address this, Taiyo Holdings developed the Material as a next-generation fine-pitch RDL material for dual damascene processes and began joint research with imec in October 2022. In November 2025, the two organizations presented a co-authored paper on the formation of a three-layer RDL structure with a CD (*4) of 1.6 micrometers on 12-inch wafers.

In this research, a three-layer RDL structure was formed on 12-inch wafers using the Material and evaluated. As a result, the target dimension of 700-nm CD was achieved for both interconnects and vias. The 700-nm CD metal 1 layer (M1) also demonstrated favorable electrical characteristics in terms of leakage current and resistance. Through this joint research with imec, it was confirmed that the Material offers excellent electrical characteristics and high resolution and is suitable for use with the CMP process (*5). These results represent an important achievement in interconnect technology for next-generation advanced packaging, paving the way for the future development of submicron-class RDL design rules.

Going forward, Taiyo Holdings aims to achieve RDL formation with a CD of 500 nm or less on wafers, while continuing to verify the long-term performance and reliability of the electrical characteristics. The company will continue developing materials that contribute to the growth of the semiconductor packaging field, such as by enabling further improvements in the performance of AI semiconductors. Taiyo Holdings also began shipping small-volume samples of the Material for R&D applications in 2025.

Notes:
(*1) RDL (redistribution layer) is a layer formed on the surface of a semiconductor chip to redistribute electrical wiring.
(*2) A method in which a thin seed layer is formed over the entire surface, followed by electroplating to form wiring patterns in designated areas.
(*3) A method in which wiring trenches are formed in an insulating film and then filled by sputtering, CVD, electroplating, or similar methods to form wiring patterns.
(*4) CD (critical dimension) refers to the dimensions of fine patterns.
(*5) The CMP process (chemical mechanical planarization/polishing) is a semiconductor-manufacturing process that chemically and mechanically planarizes the wafer surface.

- Conference information & presentation details
Name of conference: The 11th IEEE Electronics System-Integration Technology Conference
Location: Helsinki, Finland
Dates: From Wednesday, September 9, to Friday, September 11, 2026
Presentation session: MIP 1: Dielectric and Glass Materials for Advanced Substrates
Co-authored paper title: A Novel i-Line Photosensitive Dielectric Material Enabling 700 nm Polymer Damascene RDL for Advanced Packaging
Related Link: https://www.estc-conference.net/

- Partnership between imec and Taiyo Holdings
Headquartered in Belgium, imec is one of the world’s leading research and innovation hubs for advanced semiconductor technology. It promotes open innovation in collaboration with universities and companies around the world, contributing to the development of cutting-edge semiconductor technologies. In October 2022, imec and Taiyo Holdings began joint research on a fine-pitch RDL negative-tone photosensitive insulating material for damascene processes, a material for next-generation semiconductor packaging. Since November 2024, Taiyo Holdings has also dispatched personnel to be stationed at imec to facilitate closer collaboration, while conducting ongoing research and development of advanced semiconductor materials. In November 2025, the two organizations announced that they had achieved a wiring CD of 1.6 micrometers and a via CD of 2 micrometers on 12-inch wafers using the "FPIM Series" RDL material.

Image 1: Production of Evaluation Samples
https://cdn.kyodonewsprwire.jp/prwfile/release/M108899/202608274838/_prw_PI2fl_1SbJFiHz.png

Image 2: Product Image
https://cdn.kyodonewsprwire.jp/prwfile/release/M108899/202608274838/_prw_PI1fl_NExAX0Q4.png

About Taiyo Holdings Co., Ltd.: https://kyodonewsprwire.jp/attach/202608274838-O1-s1h2S4Ka.pdf

Official website: https://www.taiyo-hd.co.jp/en/index.html

Taiyo Holdings Launches Next-generation Semiconductor-packaging Material "FPIM (TM) Series," Its...

Taiyo Holdings — Thu, 13 Nov 2025 15:00:00 +0900

TOKYO, Nov. 13, 2025 /Kyodo JBN/ --
Taiyo Holdings Co. Ltd.
Taiyo Holdings Launches Next-generation Semiconductor-packaging Material "FPIM (TM) Series," Its First Successful Formation of 3-layer RDL with CD 1.6 Micrometers on 12-inch Wafer

- Paper Presented at 14th IEEE CPMT Symposium Japan (ICSJ 2025) -

On November 13, 2025, Taiyo Holdings Co., Ltd. (Securities Code: 4626; hereinafter referred to as "Taiyo Holdings"), based in Tokyo, presented a paper, co-authored with imec, one of the world’s largest semiconductor research institutions, at the 14th IEEE CPMT Symposium Japan (ICSJ2025), focusing on the "FPIM (TM) Series" (hereinafter referred to as "this material"), a negative-type photosensitive insulating material for fine-pitch RDLs (*1) designed for the damascene process, developed as a next-generation semiconductor-packaging material.

The RDL is an important technology in the most advanced structures of semiconductor packaging for more efficient electrical connections, and it is currently manufactured mainly by the semi-additive process (SAP) (*2). The damascene process (*3), imec suggests, will become essential for forming interconnections with line spacing of 1.6 micrometers or less in the future, as finer wiring is pursued. In response, Taiyo Holdings has been developing this material as a next-
generation fine-pitch RDL material for the damascene process and has been conducting joint research with imec since October 2022. In this study, a three-layer RDL structure was formed on a 12-inch wafer using this material, and evaluations were carried out. Each wiring pitch achieved the target dimensions as follows: CD (*4) 1.6 micrometers for the RDL1 layer on the wafer, CD 2.0 micrometers (with a via center-to-center pitch of CD 4.0 micrometers) for the via layer, and CD 1.6 micrometers for the RDL2 layer. These values are extremely close to the resolution limit of the low NA stepper (*5) used in this study. In addition, the evaluation results of the electrical characteristics, specifically, leakage current and resistance, of the RDL1 layer with CD 1.6 micrometers were favorable. As an outcome of this joint research with imec, it was confirmed that this material possesses excellent electrical properties, high resolution, and quality suitable for adaptation to the CMP process (*6).

In the future, the company aims to achieve the formation of RDLs on wafers with a wiring pitch of CD 500 nm or less, while continuing to verify the long-term performance of electrical characteristics and reliability. Taiyo Holdings will continue developing materials that contribute to advances in the semiconductor-packaging field, including further performance enhancement of AI semiconductors. In addition, shipment of small-quantity samples of this material for R&D purposes began in 2025.

Notes:
(*1) RDL (redistribution layer) is a layer formed on the surface of a semiconductor chip to redistribute electrical wiring.
(*2) A method in which a thin seed layer is first formed over the entire surface, and then wiring patterns are formed by electroplating on the wiring areas.
(*3) A method in which grooves for wiring are formed on an insulating film, and the grooves are filled and patterned using sputtering, CVD, electroplating, or similar processes.
(*4) CD (critical dimension) refers to the dimensions of fine patterns.
(*5) Veeco Low NA (0.16) i-line exposure system AP300 (first generation).
(*6) CMP process (chemical mechanical planarization/polishing) is a process in semiconductor manufacturing that chemically and mechanically planarizes the wafer surface.

Title of co-authored paper
Development of 1.6 micrometer Fine-Pitch RDL Damascene Process using Low-NA i-Line Stepper and a New Negative-tone Photosensitive Dielectric Material

Structure of evaluation sample: https://cdn.kyodonewsprwire.jp/prwfile/release/M108899/202511108806/_prw_PI1fl_9Rzhabg4.png

Product image: https://cdn.kyodonewsprwire.jp/prwfile/release/M108899/202511108806/_prw_PI2fl_yb3oqDfr.png

- About Collaboration between imec and Taiyo Holdings
Headquartered in Belgium, imec, which is short for "Interuniversity Microelectronics Centre," is one of the world’s largest semiconductor research institutes. It promotes open innovation by collaborating with universities and companies around the world, contributing to the development of cutting-edge semiconductor technologies. In October 2022, imec and Taiyo Holdings began joint research on a negative-type photosensitive insulating material for fine-pitch RDLs used in the damascene process --a next-generation semiconductor-packaging material. Since November 2024, Taiyo Holdings has dispatched resident researchers to imec to establish an environment for smoother collaboration and continues daily research and development of advanced semiconductor materials.

- Company Overview of Taiyo Holdings Co., Ltd.:
https://kyodonewsprwire.jp/attach/202511108806-O1-ttbIvpYv.pdf

Official website: https://www.taiyo-hd.co.jp/en/index.html